View M390S2858CTU-C7C_1269542.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

M390S2858CTU
M390S2858CTU SDRAM DIMM
PC133/PC100 Low Profile Registered DIMM
128Mx72 SDRAM DIMM with PLL & Register based on Stacked 128Mx4, 4Banks 8K Ref., 3.3V SDRAMs with SPD
GENERAL DESCRIPTION
The Samsung M390S2858CTU is a 128M bit x 72 Synchronous Dynamic RAM high density memory module. The Samsung M390S2858CTU consists of eighteen CMOS Stacked 128Mx4 bit Synchronous DRAMs in three TSOP-II 400mil packages, two 18-bits Drive ICs for input control signal, one PLL in 24-pin TSSOP package for clock and one 2K EEPROM in 8-pin TSSOP package for Serial Presence Detect on a 168pin glass-epoxy substrate. Two 0.1uF decoupling capacitors are mounted on the printed circuit board in parallel for each SDRAM. The M390S2858CTU is a Dual In-line Memory Module and is intented for mounting into 168-pin edge connector sockets. Synchronous design allows precise cycle control with the use of system clock. I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable latencies allows the same device to be useful for a variety of high bandwidth, high performance memory system applications.
FEATURE
* Performance range Part No. M390S2858CTU-C7C M390S2858CTU-C7A M390S2858CTU-C1H M390S2858CTU-C1L * * * * * Max Freq. (Speed) 133MHz (7.5ns @ CL=2) 133MHz (7.5ns @ CL=3) 100MHz (10ns @ CL=2) 100MHz (10ns @ CL=3)
Burst mode operation Auto & self refresh capability (8192 Cycles/64ms) LVTTL compatible inputs and outputs Single 3.3V 0.3V power supply MRS cycle with address key programs Latency (Access from column address) Burst length (1, 2, 4 , 8 & Full page) Data scramble (Sequential & Interleave) * All inputs are sampled at the positive going edge of the system clock * Serial presence detect with EEPROM * PCB : Height (1,200mil), double sided component
PIN CONFIGURATIONS (Front side/back side)
Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 Front VSS DQ0 DQ1 DQ2 DQ3 VDD DQ4 DQ5 DQ6 DQ7 DQ8 VSS DQ9 DQ10 DQ11 DQ12 DQ13 VDD DQ14 DQ15 CB0 CB1 VSS NC NC VDD WE DQM0 Pin Front Pin Front DQ18 DQ19 VDD DQ20 NC *VREF *CKE1 VSS DQ21 DQ22 DQ23 VSS DQ24 DQ25 DQ26 DQ27 VDD DQ28 DQ29 DQ30 DQ31 VSS *CLK2 NC NC **SDA **SCL VDD Pin Back Pin 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 Back DQM5 CS1 RAS VSS A1 A3 A5 A7 A9 BA0 A11 VDD *CLK1 A12 VSS CKE0 CS3 DQM6 DQM7 *A13 VDD NC NC CB6 CB7 VSS DQ48 DQ49 Pin Back 29 DQM1 57 58 CS0 30 59 31 DU 60 32 VSS 61 33 A0 62 34 A2 63 35 A4 64 36 A6 65 37 A8 38 A10/AP 66 67 39 BA1 68 40 VDD 69 41 VDD 42 CLK0 70 71 43 VSS 44 DU 72 73 45 CS2 46 DQM2 74 47 DQM3 75 76 48 DU 77 49 VDD 78 50 NC 79 51 NC 80 52 CB2 81 53 CB3 82 54 VSS 55 DQ16 83 56 DQ17 84 VSS 85 86 DQ32 87 DQ33 88 DQ34 89 DQ35 VDD 90 91 DQ36 92 DQ37 93 DQ38 94 DQ39 95 DQ40 96 VSS 97 DQ41 98 DQ42 99 DQ43 100 DQ44 101 DQ45 102 VDD 103 DQ46 104 DQ47 105 CB4 106 CB5 107 VSS 108 NC NC 109 110 VDD 111 CAS 112 DQM4 141 DQ50 142 DQ51 143 VDD 144 DQ52 NC 145 146 *VREF 147 REGE VSS 148 149 DQ53 150 DQ54 151 DQ55 VSS 152 153 DQ56 154 DQ57 155 DQ58 156 DQ59 157 VDD 158 DQ60 159 DQ61 160 DQ62 161 DQ63 162 VSS 163 *CLK3 NC 164 165 **SA0 166 **SA1 167 **SA2 168 VDD
PIN NAMES
Pin Name A0 ~ A12 BA0 ~ BA1 DQ0 ~ DQ63 CB0 ~ CB7 CLK0 CKE0 CS0 ~ CS3 RAS CAS WE DQM0 ~ 7 VDD VSS *VREF REGE SDA SCL SA0 ~ 2 DU NC Function Address input (Multiplexed) Select bank Data input/output Check bit (Data-in/data-out) Clock input Clock enable input Chip select input Row address strobe Colume address strobe Write enable DQM Power supply (3.3V) Ground Power supply for reference Register enable Serial data I/O Serial clock Address in EEPROM Dont use No connection
* These pins are not used in this module. ** These pins should be NC in the system which does not support SPD.
SAMSUNG ELECTRONICS CO., Ltd. reserves the right to change products and specifications without notice.
Rev. 0.1 Sept. 2001
M390S2858CTU
PIN CONFIGURATION DESCRIPTION
Pin CLK CS Name System clock Chip select
PC133/PC100 Low Profile Registered DIMM
Input Function Active on the positive going edge to sample all inputs. Disables or enables device operation by masking or enabling all inputs except CLK, CKE and DQM Masks system clock to freeze operation from the next clock cycle. CKE should be enabled at least one cycle prior to new command. Disable input buffers for power down in standby. CKE should be enabled 1CLK+tss prior to valid command. Row/column addresses are multiplexed on the same pins. Row address : RA0 ~ RA12, Column address : CA0 ~ CA9, CA11 Selects bank to be activated during row address latch time. Selects bank for read/write during column address latch time. Latches row addresses on the positive going edge of the CLK with RAS low. Enables row access & precharge. Latches column addresses on the positive going edge of the CLK with CAS low. Enables column access. Enables write operation and row precharge. Latches data in starting from CAS, WE active. Makes data output Hi-Z, tSHZ after the clock and masks the output. Blocks data input when DQM active. (Byte masking) The device operates in the transparent mode when REGE is low. When REGE is high, the device operates in the registered mode. In registered mode, the Address and control inputs are latched if CLK is held at a high or low logic level. the inputs are stored in the latch/flip-flop on the rising edge of CLK. REGE is tied to VDD through 10K ohm Resistor on PCB. So if REGE of module is floating, this module will be operated as registered mode. Data inputs/outputs are multiplexed on the same pins. Check bits for ECC. Power and ground for the input buffers and the core logic.
CKE
Clock enable
A0 ~ A12 BA0 ~ BA1 RAS CAS WE DQM0 ~ 7
Address Bank select address Row address strobe Column address strobe Write enable Data input/output mask
REGE
Register enable
DQ0 ~ 63 CB0 ~ 7 VDD/VSS
Data input/output Check bit Power supply/ground
Rev. 0.1 Sept. 2001
M390S2858CTU
BCS1
PC133/PC100 Low Profile Registered DIMM
FUNCTIONAL BLOCK DIAGRAM
PCLK0 BCS0 B0CKE0 B0A0~B0A12,B0BA0~1, B0RAS, B0CAS, B0WE BDQM0 DQ0~3 10 PCLK1 CLK CS CKE Add,CTL DQM DQ0~3 CLK CS CKE Add,CTL DQM DQ0~3 CLK CS CKE Add,CTL DQM DQ0~3 CLK CS CKE Add,CTL DQM DQ0~3 CLK CS CKE Add,CTL DQM DQ0~3 CLK CS CKE Add,CTL DQM DQ0~3 CLK CS CKE Add,CTL DQM DQ0~3 CLK CS CKE Add,CTL DQM DQ0~3 CLK CS CKE Add,CTL DQM DQ0~3
D0L
CLK CS CKE Add,CTL DQM DQ0~3 CLK CS CKE Add,CTL DQM DQ0~3 CLK CS CKE Add,CTL DQM DQ0~3 CLK CS CKE Add,CTL DQM DQ0~3 CLK CS CKE Add,CTL DQM DQ0~3 CLK CS CKE Add,CTL DQM DQ0~3 CLK CS CKE Add,CTL DQM DQ0~3 CLK CS CKE Add,CTL DQM DQ0~3 CLK CS CKE Add,CTL DQM DQ0~3
D0U
BDQM4 DQ32~35 10
CLK CS CKE Add,CTL DQM DQ0~3 CLK CS CKE Add,CTL DQM DQ0~3 CLK CS CKE Add,CTL DQM DQ0~3 CLK CS CKE Add,CTL DQM DQ0~3 CLK CS CKE Add,CTL DQM DQ0~3 CLK CS CKE Add,CTL DQM DQ0~3 CLK CS CKE Add,CTL DQM DQ0~3
D9L
CLK CS CKE Add,CTL DQM DQ0~3 CLK CS CKE Add,CTL DQM DQ0~3 CLK CS CKE Add,CTL DQM DQ0~3 CLK CS CKE Add,CTL DQM DQ0~3 CLK CS CKE Add,CTL DQM DQ0~3 CLK CS CKE Add,CTL DQM DQ0~3 CLK CS CKE Add,CTL DQM DQ0~3 CLK CS CKE Add,CTL DQM DQ0~3 CLK CS CKE Add,CTL DQM DQ0~3
D9
D1L
D1U
10 DQ36~39
D10L
D10
DQ4~7 10 PCLK2
D2L
D2U
BDQM5 DQ40~43 10
D11L
D11
BDQM1 DQ8~11 10 PCLK3
D3L
D3U
10 DQ44~47
D12L
D12
DQ12~15 10 PCLK4
D4L
D4U
10
D13L
D13
CB0~3 10 PCLK5 BCS2
CB4~7
D5L
D5U
BDQM6 DQ48~51 10
D14L
D14
BDQM2 DQ16~19 10 PCLK6
D6L
D6U
DQ52~55 10
D15L
D15
DQ20~23 10 PCLK7
D7L
D7U
BDQM7 DQ56~59 10
BDQM3 DQ24~27 10
CLK CS CKE Add,CTL DQM DQ0~3 CLK CS CKE Add,CTL DQM DQ0~3
D16L
D16
PCLK8 BCS2 B1CKE0 B1A0~B1A12,B1BA0~1, B1RAS, B1CAS, B1WE BDQM0 DQ28~31 10 BCS3
D8L
D8U
BDQM7 DQ60~63 10
D17L
D17
VSS A0~A12,BA0~1, RAS, CAS CKE0 VDD 10k PCLK9 REGE LE 74ALVCF162835 OE 10 B1A0~B1A12,B1BA0~1, B1RAS, B1CAS CLK0 12pF
CLK FIBIN
74ALVCF162835
10 12pF
2G AGND 1G AVCL
B0A0~B0A12,B0BA0~1, B0RAS, B0CAS B0CKE0 B1CKE0 CLK1,2,3
VDD
IY0 IY1 IY2 IY3 IY4 IY5 IY6 IY7 IY8 IY9 PCLK9 PCLK5 PCLK6 PCLK7 PCLK8 PCLK0 PCLK1 PCLK2 PCLK3 PCLK4
CDCF2510
FBOUT
Cb*1
LE 74ALVCF162835 WE
OE
Note 1. The actual values of Cb will depend upon the PLL chosen.
Serial PD
B0WE,B0CKE1 B1WE,B1CKE1 BDQM0~7, BCS0~3
SCL
47K
WP A0
SDA A1 A2
DQM0~7,CS0~3 LE OE
SA0 SA1 SA2
Rev. 0.1 Sept. 2001
M390S2858CTU
PC133/PC100 Low Profile Registered DIMM
STANDARD TIMING DIAGRAM WITH PLL & REGISTER (CL=2, BL=4)
*2 *1
Control Signal(RAS,CAS,WE) REG
*3 DOUT
*1. Register Input
0 CLK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
RAS CAS WE
*2. Register Output
RAS
td tr td tr
CAS WE
*3. SDRAM
CAS latency(refer to *1) =2CLK+1CLK tSAC tRAC(refer to *1)
1CLK
DQ
tRAC(refer to *2)
Qa0
Qa1
Qa2
Qa3
Db0
Db1
Db2
Db3
CAS latency(refer to *2) =2CLK
tRDL
Row Active
Read Command
Precharge Command
Row Active
Write Command
Precharge Command
td, tr = Delay of register (74ALVCF162835)
Notes : 1. In case of module timing, command cycles delayed 1CLK with respect to external input timing at the address and input signal because of the buffering in register . Therefore, Input/Output signals of read/write function should be issued 1CLK earlier as compared to Unbuffered DIMMs. 2. DIN is to be issued 1clock after write command in external timing because DIN is issued directly to module.
: Dont care
Rev. 0.1 Sept. 2001
M390S2858CTU
ABSOLUTE MAXIMUM RATINGS
Parameter Voltage on any pin relative to Vss Voltage on VDD supply relative to Vss Storage temperature Power dissipation Short circuit current
PC133/PC100 Low Profile Registered DIMM
Symbol VIN, VOUT VDD, VDDQ TSTG PD IOS Value -1.0 ~ 4.6 -1.0 ~ 4.6 -55 ~ +150 36 50 Unit V V C W mA
Note : Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded. Functional operation should be restricted to recommended operating condition. Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
DC OPERATING CONDITIONS AND CHARACTERISTICS
Recommended operating conditions (Voltage referenced to VSS = 0V, TA = 0 to 70C) Parameter Supply voltage Input high voltage Input low voltage Output high voltage Output low voltage Input leakage current Symbol VDD VIH VIL VOH VOL ILI Min 3.0 2.0 -0.3 2.4 -10 Typ 3.3 3.0 0 Max 3.6 VDDQ+0.3 0.8 0.4 10 Unit V V V V V uA 1 2 IOH = -2mA IOL = 2mA 3 Note
Notes : 1. VIH (max) = 5.6V AC. The overshoot voltage duration is 3ns. 2. VIL (min) = -2.0V AC. The undershoot voltage duration is 3ns. 3. Any input 0V VIN VDDQ. Input leakage currents include Hi-Z output leakage for all bi-directional buffers with Tri-State outputs.
CAPACITANCE
(VDD = 3.3V, TA = 23C, f = 1MHz, VREF =1.4V 200 mV) Symbol CIN1 CIN2 CIN3 CIN4 CIN5 CIN6 CIN7 COUT COUT1 Min Max 15 15 15 20 15 15 15 22 22 Unit pF pF pF pF pF pF pF pF pF
Parameter Input capacitance (A0 ~ A12) Input capacitance (RAS, CAS, WE) Input capacitance (CKE0) Input capacitance (CLK0) Input capacitance (CS0, CS2) Input capacitance (DQM0 ~ DQM7) Input capacitance (BA0 ~ BA1) Data input/output capacitance (DQ0 ~ DQ63) Data input/output capacitance (CB0 ~ CB7)
Rev. 0.1 Sept. 2001
M390S2858CTU
DC CHARACTERISTICS
PC133/PC100 Low Profile Registered DIMM
(Recommended operating condition unless otherwise noted, TA = 0 to 70C) Parameter Symbol Burst length = 1 tRC tRC(min) IO = 0 mA CKE VIL(max), tCC = 10ns CKE & CLK VIL(max), tCC = CKE VIH(min), CS VIH(min), tCC = 10ns Input signals are changed one time during 20ns CKE VIH(min), CLK VIL(max), tCC = Input signals are stable CKE VIL(max), tCC = 10ns CKE & CLK VIL(max), tCC = CKE VIH(min), CS VIH(min), tCC = 10ns Input signals are changed one time during 20ns CKE VIH(min), CLK VIL(max), tCC = Input signals are stable IO = 0 mA Page burst 4Banks activated tCCD = 2CLKs tRC tRC(min) CKE 0.2V Test Condition - 7C Operating current (One bank active) Precharge standby current in power-down mode ICC1 ICC2P ICC2PS ICC2N Precharge standby current in non power-down mode ICC2NS Active standby current in power-down mode ICC3P ICC3PS ICC3N ICC3NS 2840 Version -7A 2660 -1H 2660 -1L 2660 mA 1 Unit Note
422 74 1070
mA
mA 362 566 218 1430 902 mA mA
mA
Active standby current in non power-down mode (One bank active)
Operating current (Burst mode) Refresh current Self refresh current
ICC4
3020
3020
2840
2840
mA
1
ICC5 ICC6
5000
4640
4460
4460
mA mA
2
458
Notes : 1. Measured with outputs open. 2. Refresh period is 64ms. 3. Unless otherwise noted, input swing level is CMOS(VIH/VIL=VDDQ/VSSQ)
Rev. 0.1 Sept. 2001
M390S2858CTU
Parameter AC input levels (Vih/Vil) Input timing measurement reference level Input rise and fall time Output timing measurement reference level Output load condition
3.3V
PC133/PC100 Low Profile Registered DIMM
Value 2.4/0.4 1.4 tr/tf = 1/1 1.4 See Fig. 2
Vtt = 1.4V
AC OPERATING TEST CONDITIONS (VDD = 3.3V 0.3V, TA = 0 to 70C)
Unit V V ns V
1200 Output 870 * * * 50pF VOH (DC) = 2.4V, IOH = -2mA VOL (DC) = 0.4V, IOL = 2mA Output Z0 = 50 *
50
50pF
(Fig. 1) DC output load circuit
(Fig. 2) AC output load circuit
OPERATING AC PARAMETER
(AC operating conditions unless otherwise noted) Parameter Row active to row active delay RAS to CAS delay Row precharge time Row active time Row cycle time Last data in to row precharge Last data in to Active delay Last data in to new col. address delay Last data in to burst stop Col. address to col. address delay Number of valid output data Symbol - 7C tRRD(min) tRCD(min) tRP(min) tRAS(min) tRAS(max) tRC(min) tRDL(min) tDAL(min) tCDL(min) tBDL(min) tCCD(min) CAS latency=3 CAS latency=2 60 65 2 2 CLK + tRP 1 1 1 2 1 15 15 15 45 15 20 20 45 100 70 70 Version - 7A - 1H 20 20 20 50 -1L 20 20 20 50 ns ns ns ns us ns CLK CLK CLK CLK ea 1 2,5 5 2 2 3 4 1 1 1 1 Unit Note
Notes : 1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then rounding off to the next higher integer. 2. Minimum delay is required to complete write. 3. All parts allow every cycle column address change. 4. In case of row precharge interrupt, auto precharge and read burst stop. 5. In 100MHz and below 100MHz operating conditions, tRDL=1CLK and tDAL=1CLK + 20ns is also supported. SAMSUNG recommends tRDL=2CLK and tDAL=2CLK + tRP.
Rev. 0.1 Sept. 2001
M390S2858CTU
PC133/PC100 Low Profile Registered DIMM
AC CHARACTERISTICS (AC operating conditions unless otherwise noted) REFER TO THE INDIVIDUAL COMPONENET, NOT THE WHOLE MODULE.
Parameter CLK cycle time CLK to valid output delay Output data hold time CAS latency=3 CAS latency=2 CAS latency=3 CAS latency=2 CAS latency=3 CAS latency=2 tCH tCL tSS tSH tSLZ tSHZ tOH 3 3 2.5 2.5 1.5 0.8 1 5.4 5.4 tSAC Symbol Min tCC 7.5 7.5 5.4 5.4 3 3 2.5 2.5 1.5 0.8 1 5.4 6 - 7C Max 1000 Min 7.5 10 5.4 6 3 3 3 3 2 1 1 6 6 - 7A Max 1000 Min 10 10 6 6 3 3 3 3 2 1 1 6 7 ns ns ns ns ns ns 3 3 3 3 2 - 1H Max 1000 Min 10 12 6 7 ns 2 ns 1,2 - 1L Max 1000 ns 1 Unit Note
CLK high pulse width CLK low pulse width Input setup time Input hold time CLK to output in Low-Z CLK to output in Hi-Z CAS latency=3 CAS latency=2
Notes : 1. Parameters depend on programmed CAS latency. 2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter. 3. Assumed input rise and fall time (tr & tf) = 1ns. If tr & tf is longer than 1ns, transient time compensation should be considered, i.e., [(tr + tf)/2-1]ns should be added to the parameter.
Rev. 0.1 Sept. 2001
M390S2858CTU
SIMPLIFIED TRUTH TABLE
Command Register Mode register set Auto refresh Refresh Entry Self refresh Exit L H H
CKEn-1
PC133/PC100 Low Profile Registered DIMM
CKEn CS RAS CAS WE DQM BA0,1 A10/AP A12,A11, A9 ~ A0 Note
H H
X H L H X X
L L L H
L L H X L H
L L H X H L
L H H X H H
X X
OP code X
1,2 3 3
X X X V V
X Row address L H
Column address (A0~A9, A11) Column address (A0~A9, A11)
3 3
Bank active & row addr. Read & column address Write & Column Address Burst stop Precharge Bank selection All banks Clock suspend or active power down Entry Exit Entry Precharge power down mode Exit DQM No operation command Auto precharge disable Auto precharge enable Auto precharge disable Auto precharge enable
L L
4 4,5 4 4,5 6
H H H
X X X
L L L H L
H H L X V X X H X V
L H H X V X X H X V
L L L X V X X H X V
X X X
V
L H X
V X
L H
X
H L H
L H L
X X X X X X V X X 7
X H L
L H H
H
H L
X
H L
X H
X H
X H
X
(V=Valid, X=Dont care, H=Logic high, L=Logic low) Notes : 1. OP Code : Operand code A0 ~ A12 & BA0 ~ BA1 : Program keys. (@ MRS) 2. MRS can be issued only at all banks precharge state. A new command can be issued after 2 clock cycles of MRS. 3. Auto refresh functions are as same as CBR refresh of DRAM. The automatical precharge without row precharge command is meant by "Auto". Auto/self refresh can be issued only at all banks precharge state. 4. BA0 ~ BA1 : Bank select addresses. If both BA0 and BA1 are "Low" at read, write, row active and precharge, bank A is selected. If both BA0 is "High" and BA1 is "Low" at read, write, row active and precharge, bank B is selected. If both BA0 is "Low" and BA1 is "High" at read, write, row active and precharge, bank C is selected. If both BA0 and BA1 are "High" at read, write, row active and precharge, bank D is selected. If A10/AP is "High" at row precharge, BA0 and BA1 is ignored and all banks are selected. 5. During burst read or write with auto precharge, new read/write command can not be issued. Another bank read/write command can be issued after the end of burst. New row active of the associated bank can be issued at tRP after the end of burst. 6. Burst stop command is valid at every burst length. 7. DQM sampled at positive going edge of a CLK and masks the data-in at the very CLK (Write DQM latency is 0), but makes Hi-Z state the data-out of 2 CLK cycles after. (Read DQM latency is 2)
Rev. 0.1 Sept. 2001
M390S2858CTU
PACKAGE DIMENSIONS
PC133/PC100 Low Profile Registered DIMM
Units : Inches (Millimeters)
5.250 (133.350) 0.118 (3.000) 5.014 (127.350)
PLL
0.054 (1.372)
R 0.079 (R 2.000) 0.157 0.004 (4.000 0.100) 0.700 (17.780)
1.200 (30.48)
(3.000)
REG REG
0.118
.118DIA 0.004 (3.000DIA 0.100) 0.350 (8.890)
0.250 (6.350) .450 (11.430) 1.450 (36.830) 4.550 (115.57)
0.250 (6.350) 2.150 (54.61)
0.100 Min
A
B
C
(2.540 Min)
0.254 Max (6.452 Max)
REG
(3.99 Min)
0.157 Min
0.050 0.0039 (1.270 0.10)
0.250 (6.350)
0.250 (6.350) 0.123 0.005 (3.125 0.125) 0.079 0.004 (2.000 0.100)
(2.540 Min)
0.100 Min
0.039 0.002 (1.000 0.050) 0.008 0.006 (0.200 0.150) 0.050 (1.270)
0.123 0.005 (3.125 0.125) 0.079 0.004 (2.000 0.100)
Detail A Tolerances : 0.005(.13) unless otherwise specified
Detail B
Detail C
SDRAM Part No. : K4S560632C - The used device is stacked 128Mx4 SDRAM - Staktek' stacking technology is Samsung' stacking technology of choice s s This module is based on JEDEC PC133 Specification
Rev. 0.1 Sept. 2001
M390S2858CTU
M390S2858CTU-C7C/C7A/C1H/C1L
*Organization : 128MX72 *Composition : 128MX4 * 18ea *Used component part # : K4S510632C *# of banks in module : 2 Rows *# of banks in component : 4 banks *Feature : 1,200 mil height & double sided *Refresh : 8K/64ms *Contents :
Byte # 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 Function described
PC133/PC100 Low Profile Registered DIMM
Function Supported -7C -7A -1H -1L -7C
Hex value -7A 80h 08h 04h 0Dh 0Bh 02h 48h 00h 01h -1H -1L
Note
# of bytes written into serial memory at module manufacturer Total # of bytes of SPD memory device Fundamental memory type # of row address on this assembly # of column address on this assembly # of module Rows on this assembly Data width of this assembly ...... Data width of this assembly Voltage interface standard of this assembly SDRAM cycle time from clock @CAS latency of 3 SDRAM access time from clock @CAS latency of 3 DIMM configuration type Refresh rate & type Primary SDRAM width Error checking SDRAM width Minimum clock delay for back-to-back random column address SDRAM device attributes : Burst lengths supported SDRAM device attributes : # of banks on SDRAM device SDRAM device attributes : CAS latency SDRAM device attributes : CS latency SDRAM device attributes : Write latency SDRAM module attributes 7.5ns 5.4ns
128bytes 256bytes (2K-bit) SDRAM 13 11 2 row 72 bits LVTTL 10ns 6ns ECC 7.8us, support self refresh x4 x4 tCCD = 1CLK 1, 2, 4, 8 & full page 4 banks 2&3 0 CLK 0 CLK Registered/Buffered DQM, address & control inputs and On-card PLL +/- 10% voltage tolerance, 10ns 6ns 10ns 6ns 75h 54h 75h 54h
1 1
A0h 60h 02h 82h 04h 04h 01h 8Fh 04h 06h 01h 01h 1Fh
A0h 60h
2 2
22
SDRAM device attributes : General
Burst Read Single bit Write precharge all, auto precharge 7.5ns 5.4ns 10ns 6ns 15ns 15ns 15ns 45ns 20ns 15ns 20ns 45ns 20ns 20ns 20ns 50ns 20ns 20ns 20ns 50ns 0Fh 0Fh 0Fh 2Dh 14h 0Fh 14h 2Dh 10ns 6ns 12ns 7ns 75h 54h A0h 60h
0Eh
23 24 25 26 27 28 29 30 31 32 33 34
SDRAM cycle time @CAS latency of 2 SDRAM access time @CAS latency of 2 SDRAM cycle time @CAS latency of 1 SDRAM access time @CAS latency of 1 Minimum row precharge time (=tRP) Minimum row active to row active delay (tRRD) Minimum RAS to CAS delay (=tRCD) Minimum activate precharge time (=tRAS) Module Row density Command and Address signal input setup time Command and Address signal input hold time Data signal input setup time
A0h 60h 00h 00h 14h 14h 14h 32h 80h
C0h 70h
2 2
14h 14h 14h 32h
2 Row of 512MB 1.5ns 0.8ns 1.5ns 1.5ns 0.8ns 1.5ns 2ns 1ns 2ns 2ns 1ns 2ns 15h 08h 15h 15h 08h 15h
20h 10h 20h
20h 10h 20h
Rev. 0.1 Sept. 2001
M390S2858CTU
Byte # 35 36~61 62 63 64 65~71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95~98 99~125 126 127 128+ Function Described
PC133/PC100 Low Profile Registered DIMM
Function Supported -7C -7A 0.8ns Intel Rev 1.2B Samsung Samsung Onyang Korea M 3 Blank 9 0 S 2 8 5 8 C T U "-" C 7 C 7 A Blank U C-die (4th Gen.) Undefined 100MHz Detailed PC100 Information Undefined 8Fh 8Fh 1 H 1 L 37h 43h 37h 41h 20h 55h 43h 64h 8Fh 8Dh 3 3 4 FCh 3Dh CEh 00h 01h 4Dh 33h 20h 39h 30h 53h 32h 38h 35h 38h 43h 54h 55h 2Dh 43h 31h 48h 31h 4Ch -1H 1ns -1L 1ns -7C 08h Hex value -7A 08h 00h 12h A4h D4h -1H 10h -1L 10h Note
Data signal input hold time Superset information (maybe used in future) SPD data revision code Checksum for bytes 0 ~ 62 Manufacturer JEDEC ID code ...... Manufacturer JEDEC ID code Manufacturing location Manufacturer part # (Memory module) Manufacturer part # (DIMM Configuration) Manufacturer part # (Data bits) ...... Manufacturer part # (Data bits) ...... Manufacturer part # (Data bits) Manufacturer part # (Mode & operating voltage) Manufacturer part # (Module depth) ...... Manufacturer part # (Module depth) Manufacturer part # (Refresh, #of banks in Comp. & Interface) Manufacturer part # (Composition component) Manufacturer part # (Component revision) Manufacturer part # (Package type) Manufacturer part # (PCB revision & type) Manufacturer part # (Hyphen) Manufacturer part # (Power) Manufacturer part # (Minimum cycle time) Manufacturer part # (Minimum cycle time) Manufacturer part # (TBD) Manufacturer revision code (For PCB) ...... Manufacturer revision code (For component) Manufacturing date (Year) Manufacturing date (Week) Assembly serial # Manufacturer specific data (may be used in future) System frequency for 100MHz PC100 specification details Unused storage locations
0.8ns
Note : 1. The row select address is excluded in counting the total # of addresses. 2. This value is based on the component specification. 3. These bytes are programmed by code of Date Week & Date Year with BCD format. 4. These bytes are programmed by Samsung' own Assembly Serial # system. All modules may have different unique serial #. s 5. These bytes are Undefined and can be used for Samsung' own purpose. s
Rev. 0.1 Sept. 2001

▲Up To Search▲

Price & Availability of M390S2858CTU-C7C

	To Download M390S2858CTU-C7C Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .